1. Field of the Invention
Embodiments of the present invention relate to an integrated circuit, and a semiconductor die package formed therefrom, including solder columns for adding structural support to the package during fabrication.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die may be mounted. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), and shrink small outline packages (SSOP). Components in a conventional leadframe package are shown in FIG. 1. The illustrated components may be used for example in a TSOP package. The package 20 includes a pair of semiconductor die 22 mounted on a leadframe 24. The die 22 are wire bonded with wires 34 to electrical leads 26 and 28 of the leadframe. In embodiments, electrical leads 26 may be angled so as to provide a down-set configuration. After the wire-bond process, semiconductor die 22, wire-bonds 34 and portions of leads 26 and 28 may be encapsulated in molding compound 30 in a known process to form the semiconductor die package 20.
TSOP package 20 may often be included as part of a system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate such as a printed circuit board. The substrate may in general include a rigid, dielectric base having a conductance pattern, generally of copper or copper alloy, etched on respective sides. For example, referring to prior art FIG. 2, the TSOP package 20 may be surface mounted along with other electronic components to a substrate such as a printed circuit board 32 in a known surface mount process. Once electrical connections between the package 20, other electronic components and the substrate 32 are made, the assembly is then typically encased in a molding compound 34 in a transfer molding process (shown taking place in FIG. 2) to form a protected SiP semiconductor package.
During the transfer molding process, the molding machine may output an injection force typically about 0.8 tons to drive the molding compound 34 into the mold cavity and around the surface mounted components. A problem in conventional transfer molding processes is that the molding compound 34 travels more quickly over the top of surface mounted components, such as TSOP package 20, than into the space between the bottom surface of the component and the printed circuit board 32, as shown in FIG. 2. With the high pressure of the transfer molding process, the molding compound above the TSOP package 20 generates large forces down on the top of the package (indicated by arrows A). For die packages having a footprint of about 4.5 mm by 2.5 mm, the forces down on the top of package 20 may be on the order of about 1.2 kgf/mm2. As there is a void beneath the package during the molding process, these forces generate large stresses within the TSOP package 20.
In the past, the die within the packages were better able to withstand these stresses generated during the transfer molding process. However, the constant drive toward smaller form factor packages require very thin die. It is presently known to employ wafer backgrind during the semiconductor fabrication process to thin die to a range of about 2 mils to 13 mils. At these thicknesses, the die are often not able to withstand the stresses generated during the molding process and they may crack. Die cracking under the stress of the molding process will generally result in the package having to be discarded. Occurring after the TSOP package fabrication process, and at the end of the SiP package fabrication process, this is an especially costly and burdensome problem.